• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention enables burn-in testing of semiconductor chips at the wafer level. To this end, the present invention, unlike conventional methods of performing burn-in tests after fabricating and packaging semiconductor chips, performs burn-in tests at the wafer level. A burn-in test board having a batch structure in which a wafer-level semiconductor chip can be freely fixed and mounted can be manufactured.The wafer-level semiconductor chips are electrically connected to the fabricated burn-in test board and fixedly mounted thereon. By performing the burn-in test, waste of packaging process time and waste of materials due to unnecessary packaging can be effectively prevented.
    公开号:KR20030020531A
    申请号:KR1020010053665
    申请日:2001-09-01
    公开日:2003-03-10
    发明作者:박계찬
    申请人:동부전자 주식회사；
    IPC主号:
    专利说明:

    Burn-in test board and manufacturing method thereof and semiconductor chip burn-in test method using the same {BOARD FOR BURN-IN TEST AND FABRICATION METHOD THEREOF, METHOD FOR TESTING SEMICONDUCTOR CHIP BY USING IT}
    [10] The present invention relates to a semiconductor chip, and more particularly, to a semiconductor chip burn-in test board suitable for burn-in testing a fabricated semiconductor chip in a wafer state, a method for manufacturing the same, and a semiconductor chip burn-in test method using the same.
    [11] As is well known, semiconductor chips fabricated on a wafer through numerous processes undergo various tests, such as AC, DC, burn-in tests, etc. to determine good quality after completion of the manufacturing. Only semiconductor chips identified as good products are shipped for use for a particular purpose.
    [12] To this end, conventionally, after conducting the AC and DC tests on the completed semiconductor chips, only the semiconductor chips determined as good products are selected and packaged, and the packaged semiconductor chips are burned-in again, and finally, the good semiconductor chips are finally manufactured. The bay is classified.
    [13] Here, packaging means packaging semiconductor wafers (multi-chip packaging, chip scale packaging, etc.) by performing various processes (deposition process, etching process, patterning process, etc.), and such packaging process Among them, defects may occur in good quality semiconductor chips due to various factors.
    [14] Therefore, in the conventional method in which the wafer-level semiconductor chip is packaged first and then burn-in test is performed, the burn-in test is performed after packaging, resulting in unnecessary packaging of the semiconductor chip determined as defective. As a result, waste of processing time and waste of materials for packaging are used to increase the price of semiconductor chips.
    [15] Disclosure of Invention The present invention has been made to solve the above-mentioned problems of the prior art, and an object thereof is to provide a burn-in test board and a method of manufacturing the same that can burn-in a semiconductor chip at a wafer level.
    [16] It is another object of the present invention to provide a semiconductor chip burn-in test method which can burn-in a semiconductor chip at a wafer level.
    [17] According to an aspect of the present invention, there is provided a burn-in test board for performing a burn-in test of a semiconductor chip at a wafer level, comprising: a substrate; A plurality of electrode wirings having a predetermined pattern on the substrate and having a predetermined thickness and electrically insulated from each other; A plurality of electrodes formed on one end of each of the electrode wires to have a predetermined thickness and contacting corresponding pads of each semiconductor chip to be tested; And it is formed in the form of covering each of the electrode wiring and the substrate, and provides a burn-in test board made of an adhesive bonded to a portion of the lower surface of each semiconductor chip to be tested.
    [18] According to another aspect of the present invention, there is provided a method of manufacturing a burn-in test board for performing a burn-in test of a semiconductor chip at a wafer level, the method comprising: forming an electrode wiring material on a substrate; Selectively removing a portion of the electrode wiring material through an etching process using an arbitrary pattern mask to selectively expose a portion of the upper portion of the substrate, thereby forming a plurality of electrode wirings electrically insulated from each other; Forming a photoresist pattern for selectively exposing one end of each electrode wiring; Forming an electrode having a predetermined thickness to be bonded to each pad of the semiconductor chip for a test at one end of each exposed electrode wiring, and then removing the photoresist pattern; And it provides a burn-in test board manufacturing method comprising the step of forming an adhesive to be bonded to the lower portion of the semiconductor chip in the entire area except the electrode and a portion of the substrate.
    [19] According to another aspect of the present invention, there is provided a method of burn-in testing a semiconductor chip at a wafer level using a burn-in test board, wherein the plurality of electrode wirings having an arbitrary pattern and are electrically insulated from each other. Forming a substrate on the substrate; Forming electrodes of a predetermined thickness on one end of each electrode wiring; Forming an adhesive to be adhered to the lower portion of the semiconductor chip in the entire region except for each of the electrodes and the substrate; Arranging a plurality of semiconductor chips on the substrate such that each pad in each semiconductor chip corresponds to each corresponding electrode; Bonding each pad and a corresponding electrode and bonding a lower portion of each semiconductor chip to the adhesive through a bonding process at any process condition; Performing a burn-in test with a plurality of semiconductor chips adhered to the substrate; And a process of releasing the bonding force between the respective pads and the respective electrodes and the adhesive force of the adhesive through the isolation process under arbitrary process conditions.
    [1] 1 is a partially cutaway plan view of a semiconductor chip burn-in test board according to an exemplary embodiment of the present disclosure;
    [2] 2a to 2f is a process flowchart showing a process of manufacturing a burn-in test board according to a preferred embodiment of the present invention,
    [3] 3 is a partially cutaway cross-sectional view illustrating a process of performing a burn-in test of a semiconductor chip at a wafer level using a burn-in test board manufactured according to the present invention.
    [4] <Description of the symbols for the main parts of the drawings>
    [5] 100 substrate 102 seed layer
    [6] 104 diffusion barrier layer 106 reinforcement layer
    [7] 110: electrode wiring 114: electrode
    [8] 116: adhesive 200: semiconductor chip
    [9] 202: Pad
    [20] The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.
    [21] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
    [22] A key technical aspect of the present invention is that, unlike a conventional method of performing burn-in test after manufacturing and packaging a semiconductor chip, a batch structure in which the wafer-level semiconductor chip can be freely fixed and mounted so as to perform burn-in test at the wafer level. By manufacturing a burn-in test board having a, and electrically mounting the wafer-level semiconductor chips to the fabricated burn-in test board to perform a burn-in test at the wafer level, in the present invention through such technical means It is easy to achieve the purpose.
    [23] 1 is a partially cutaway view of a plane of a semiconductor chip burn-in test board according to a preferred embodiment of the present invention.
    [24] Referring to FIG. 1, in the burn-in test board of the present invention, a plurality of electrode wires 110 are electrically insulated from each other on a substrate 100, and one end (ie, one end) of each electrode wires 110 is formed. There are formed electrodes 114 each having a predetermined height, each electrode 114 having corresponding respective pads of a semiconductor chip (i.e., wafer-level semiconductor chip) to be mounted on the substrate 100 for burn-in testing. Are glued. At this time, although not shown in the drawings, the other end of each electrode wiring 110 (the other end of the electrode is not formed) is electrically connected to one output node of each electronic circuit for burn-in test of the semiconductor chip.
    [25] Here, as the material of the substrate 100, for example, FR4, FR5, BT resin series may be used, the thickness is preferably in the range of 0.7mm to 3mm.
    [26] In addition, as each electrode 114 formed at one end of the electrode wiring, for example, Au, Ta, Cr, Co and the like can be used, the shape can be round or square, the thickness is 2mil to 4mil Preferably, the diameter is 1 mil to 4 mils in the case of a round shape, and 1 mil x 1 mil to 4 mils × 4 mil in a square shape.
    [27] Meanwhile, the burn-in test board includes a substrate 100 and an upper portion of the substrate 100 in the middle portion of two electrode groups facing each other (ie, the electrode group formed in the upper part and the electrode group formed in the lower part in series in FIG. 1). Except for 114, the remaining portions (ie, the upper portion of the electrode wiring and the upper portion of the remaining substrate) are covered with the adhesive 116.
    [28] Here, the adhesive 116 is bonded to the lower surface of the semiconductor chip to be mounted for burn-in test, that is, a part of the surface on which the pads are formed, and the half curing occurs at about 125 ° C. or more and the semiconductor chip at about 150 ° C. or more. Epoxy or polyimide-based resin having a property capable of separating (isolating) may be used, and the thickness thereof is preferably 2.2 mils to 4.2 mils in consideration of the thickness of the electrode 114.
    [29] FIG. 2F is a cross-sectional view taken along the line A-A shown in FIG. 1.
    [30] Referring to FIG. 2F, each electrode wiring 110 employed in the burn-in test board according to the present invention may include a seed layer 102, a diffusion barrier layer 104, and a reinforcement layer 106 sequentially stacked on the substrate 100. It has a multilayer structure.
    [31] Here, for example, Cu having a thickness range of about 10 μm to 4 mils may be used as the seed layer 102, and as the diffusion barrier layer 104, for example, about 5 μm to 2 mils. Ni having a thickness range may be used, and as the reinforcing layer 106, for example, W, Ti, W / Ti, or the like having a thickness range of about 5 μm to 2 mil may be used.
    [32] Next, the process of manufacturing the self-test board having the structure as described above according to the present invention will be described.
    [33] 2A to 2F are process flowcharts illustrating a process of manufacturing a burn-in test board according to a preferred embodiment of the present invention.
    [34] Referring to FIG. 2A, a seed material 102a, a diffusion barrier material 104a, and a reinforcing material 106a are sequentially formed on the substrate 100 by using a method such as sputtering and evaporation.
    [35] Here, as the seed material 102a, for example, Cu having a thickness range of about 10 μm to 4 mil may be used, and as the diffusion barrier material 104a, for example, a thickness range of about 5 μm to 2 mil Ni and the like may be used, and as the reinforcing material 106a, for example, W, Ti, W / Ti, or the like having a thickness range of about 5 μm to 2 mil may be used.
    [36] Next, by applying a photoresist over the entire upper surface of the reinforcing material 106a and then performing an exposure and development process, as an example, as shown in FIG. 2B, a pattern for exposing the upper portion of the seed material 106a The mask 108 is formed.
    [37] Subsequently, through the etching process using the pattern mask 108 as an etching barrier layer, the reinforcing material 102a, the diffusion barrier material 104a, and the seed material 106a are sequentially removed to expose the upper portion of the substrate 100. By removing the pattern mask 108, as shown in FIG. 2C, for example, the electrode wiring 110 of the seed layer 102, the diffusion barrier layer 104, and the reinforcement layer 106, that is, any pattern, may be removed. And a plurality of electrode wires which are electrically insulated from each other are formed on the substrate 100.
    [38] Again, by applying the photoresist in the form of completely filling the metal wiring 110, and then performing the exposure and development process, as shown in Figure 2d as an example, one end (that is, each of each metal wiring 110) A photoresist pattern 112 is formed to expose one end of the metal wiring.
    [39] Subsequently, the top of the seed layer 106 exposed to a material such as Au, Ta, Cr, or Co may be raised to the height of the photoresist pattern 112 by using an electroplating or electroless plating method or a sputtering or evaporation method. By removing the photoresist pattern 112 after embedding, for example, as shown in FIG. 2E, electrodes 114 are formed on one end of each electrode wiring 110, respectively.
    [40] Here, the electrode 114 may be formed in a circular or square shape having a thickness of 2 mil to 4 mil, and when the shape is circular, the size is preferably 1 mil to 4 mil in diameter, and the size when the shape is rectangular. Is preferably 1 mil × 1 mil to 4 mil × 4 mils.
    [41] Finally, by using a method such as screen printing, the upper portion and the upper portion of the substrate 100 of the middle portion of the two electrode groups (that is, the electrode group formed in the upper portion and the electrode group formed in the lower portion in series in Figure 1) By covering the remaining portions except the electrodes 114 (that is, the top of the electrode wiring and the top of the remaining substrate) with the adhesive 116, the manufacture of the burn-in test board is completed as an example, as shown in FIG. 2F.
    [42] At this time, the adhesive 116 used is bonded to the lower surface of the semiconductor chips mounted on the board for burn-in test, that is, a part of the surface on which the pads are formed. Half curing occurs at about 125 ° C. or more and is approximately 150 ° C. As described above, an epoxy or polyimide resin having a property of detaching (isolating) a semiconductor chip may be used, and the thickness thereof is preferably about 2.2 mils to 4.2 mils in consideration of the thickness of the electrode 114. .
    [43] Next, a process of performing a burn-in test of a semiconductor chip at the wafer level using a burn-in test board manufactured through a series of processes described above will be described.
    [44] 3 is a partial cutaway cross-sectional view illustrating a process of performing a burn-in test of a semiconductor chip at a wafer level using a burn-in test board manufactured according to the present invention.
    [45] Referring to FIG. 3, after the semiconductor chip 200 on which the plurality of pads 202 are formed is aligned with the upper surface of the substrate 100, that is, between the respective pads 202 and the corresponding electrodes 114, The semiconductor chip 200 is adhered to the substrate 100 by performing a bonding (gluing) process for a predetermined time at a temperature of 125 ° C. or higher.
    [46] At this time, the corresponding pad 202 and the electrode 114 are flip chip bonded, and a lower portion of the semiconductor chip 200 except for the pad 202 is adhered to the adhesive 116.
    [47] Therefore, a plurality of semiconductor chips (wafer level semiconductor chips) are mounted on the burn-in test board through the process as described above, and then burn-in tests are performed.
    [48] Subsequently, when the burn-in test is completed, the semiconductor chip 200 adhered to the substrate 100 may be removed by performing a separation process for a predetermined time (for example, about 30 minutes) at a temperature condition of 150 ° C. or higher. ), The burn-in test process is completed.
    [49] After that, by classifying the semiconductor chips determined as good and performing a package process, each semiconductor chip of the good product will be used as a multichip package, a multichip module, a stack chip package, a bump chip, and the like.
    [50] That is, in the present invention, after performing the burn-in test of the semiconductor chip at the wafer level, it is determined whether the product is good or not, and only the semiconductor chips determined as the good product are selected for the packaging process.
    [51] As described above, according to the present invention, unlike the conventional method of manufacturing and packaging a semiconductor chip and carrying out a burn-in test, an arrangement capable of detachably fixing and mounting a wafer-level semiconductor chip so as to perform a burn-in test at the wafer level. Packaging process time due to unnecessary packaging by fabricating a burn-in test board having a structure, electrically connecting wafer-level semiconductor chips to the fabricated burn-in test board, and performing burn-in tests at the wafer level. Waste and material waste can be effectively prevented.
    权利要求:
    Claims (41)
    [1" claim-type="Currently amended] A burn-in test board for performing burn-in tests of semiconductor chips at the wafer level,
    Board;
    A plurality of electrode wirings having a predetermined pattern on the substrate and having a predetermined thickness and electrically insulated from each other;
    A plurality of electrodes formed on one end of each of the electrode wires to have a predetermined thickness and contacting corresponding pads of each semiconductor chip to be tested; And
    The burn-in test board is formed in a form covering the electrode wiring and a portion of the substrate, the adhesive board is bonded to a portion of the lower surface of each semiconductor chip to be tested.
    [2" claim-type="Currently amended] The burn-in test board according to claim 1, wherein the substrate is FR4, FR5 or BT resin.
    [3" claim-type="Currently amended] The burn-in test board according to claim 2, wherein the thickness range of the substrate is 0.7 mm to 3 mm.
    [4" claim-type="Currently amended] The method of claim 1, wherein the electrode wiring is:
    A seed layer formed on the substrate;
    A diffusion barrier layer formed on the seed layer; And
    Burn-in test board comprising a reinforcing layer formed on top of the diffusion barrier layer.
    [5" claim-type="Currently amended] The burn-in test board according to claim 4, wherein the seed layer is copper.
    [6" claim-type="Currently amended] The burn-in test board of claim 5, wherein the seed layer has a thickness in a range of 10 μm to 4 mil.
    [7" claim-type="Currently amended] The burn-in test board according to claim 4, wherein the diffusion barrier layer is Ni.
    [8" claim-type="Currently amended] 8. The burn-in test board according to claim 7, wherein the diffusion barrier layer has a thickness in a range of 5 µm to 2 mil.
    [9" claim-type="Currently amended] The burn-in test board according to claim 4, wherein the reinforcement layer is W, Ti, or W / Ti.
    [10" claim-type="Currently amended] 10. The burn-in test board according to claim 9, wherein the reinforcement layer has a thickness in a range of 5 µm to 2 mil.
    [11" claim-type="Currently amended] The burn-in test board according to claim 1, wherein each electrode is Au, Ta, Cr, or Co.
    [12" claim-type="Currently amended] 12. The burn-in test board according to claim 11, wherein each electrode is circular.
    [13" claim-type="Currently amended] 13. The burn-in test board according to claim 12, wherein each electrode has a thickness in the range of 2 mil to 4 mil and a diameter in the range of 1 mil to 4 mil.
    [14" claim-type="Currently amended] 12. The burn-in test board according to claim 11, wherein each electrode is rectangular.
    [15" claim-type="Currently amended] 15. The burn-in test board according to claim 14, wherein each electrode has a thickness in the range of 2 mil to 4 mils and a size in the range of 1 mil x 1 mil to 4 mil x 4 mil.
    [16" claim-type="Currently amended] The burn-in test board according to claim 1, wherein the adhesive is a resin having a property of being half-cured at 125 ° C or higher and isolated from the semiconductor chip at 150 ° C or higher.
    [17" claim-type="Currently amended] The burn-in test board according to claim 1 or 16, wherein the component of the adhesive is an epoxy or polyimide resin.
    [18" claim-type="Currently amended] A method of manufacturing a burn-in test board for performing burn-in tests of semiconductor chips at the wafer level,
    Forming an electrode wiring material on the substrate;
    Selectively removing a portion of the electrode wiring material through an etching process using an arbitrary pattern mask to selectively expose a portion of the upper portion of the substrate, thereby forming a plurality of electrode wirings electrically insulated from each other;
    Forming a photoresist pattern for selectively exposing one end of each electrode wiring;
    Forming an electrode having a predetermined thickness to be bonded to each pad of the semiconductor chip for a test at one end of each exposed electrode wiring, and then removing the photoresist pattern; And
    A method of manufacturing a burn-in test board comprising a process of forming an adhesive to be attached to a lower portion of the semiconductor chip in the entire region except for each of the electrodes and the substrate.
    [19" claim-type="Currently amended] The burn-in test board manufacturing method according to claim 18, wherein the substrate is FR4, FR5 or BT resin.
    [20" claim-type="Currently amended] 20. The method for manufacturing a burn-in test board according to claim 19, wherein the thickness range of the substrate is 0.7 mm to 3 mm.
    [21" claim-type="Currently amended] 19. The method of claim 18, wherein the electrode wiring material is:
    A seed material formed on top of the substrate;
    A diffusion barrier material formed on top of the seed material; And
    And a reinforcing material formed on top of said diffusion barrier material.
    [22" claim-type="Currently amended] 22. The method of claim 21 wherein the seed material is copper.
    [23" claim-type="Currently amended] 23. The method of claim 22 wherein the thickness of the seed material ranges from 10 microns to 4 mils.
    [24" claim-type="Currently amended] 22. The method of claim 21 wherein the diffusion barrier material is Ni.
    [25" claim-type="Currently amended] 25. The method of claim 24 wherein the thickness of the diffusion barrier material ranges from 5 microns to 2 mils.
    [26" claim-type="Currently amended] The method of claim 21, wherein the reinforcing material is W, Ti, or W / Ti.
    [27" claim-type="Currently amended] The method of claim 26, wherein the thickness of the reinforcing material ranges from 5 microns to 2 mils.
    [28" claim-type="Currently amended] The burn-in test board manufacturing method according to claim 18, wherein each electrode is Au, Ta, Cr or Co.
    [29" claim-type="Currently amended] 29. The method of manufacturing a burn-in test board according to claim 28, wherein each electrode is circular.
    [30" claim-type="Currently amended] 30. The method of claim 29, wherein each electrode has a thickness in the range of 2 mils to 4 mils and a diameter in the range of 1 mils to 4 mils.
    [31" claim-type="Currently amended] 29. The method of claim 28, wherein each electrode is rectangular
    [32" claim-type="Currently amended] 32. The method of claim 31 wherein each electrode has a thickness in the range of 2 mils to 4 mils and a size in the range of 1 mil x 1 mil to 4 mil x 4 mils.
    [33" claim-type="Currently amended] 19. The method as claimed in claim 18, wherein the adhesive is a resin having a property of being half cured at 125 ° C or higher and isolated from the semiconductor chip at 150 ° C or higher.
    [34" claim-type="Currently amended] The burn-in test board manufacturing method according to claim 18, wherein the adhesive is formed by a screen printing method.
    [35" claim-type="Currently amended] The method of claim 34, wherein the adhesive is formed at least higher than the height of each electrode.
    [36" claim-type="Currently amended] 36. The method for manufacturing a burn-in test board according to claim 18, 33, 34 or 35, wherein the component of the adhesive is an epoxy or polyimide resin.
    [37" claim-type="Currently amended] In the method for burn-in testing a semiconductor chip at the wafer level using a burn-in test board,
    Forming a plurality of electrode wirings having an arbitrary pattern and electrically insulated from each other on a substrate;
    Forming electrodes of a predetermined thickness on one end of each electrode wiring;
    Forming an adhesive to be adhered to the lower portion of the semiconductor chip in the entire region except for each of the electrodes and the substrate;
    Arranging a plurality of semiconductor chips on the substrate such that each pad in each semiconductor chip corresponds to each corresponding electrode;
    Bonding each pad and a corresponding electrode and bonding a lower portion of each semiconductor chip to the adhesive through a bonding process at any process condition;
    Performing a burn-in test with a plurality of semiconductor chips adhered to the substrate; And
    A semiconductor chip burn-in test method comprising the step of releasing the bonding force between the respective pad and the corresponding electrode and the adhesive force of the adhesive through the isolation process under any process conditions.
    [38" claim-type="Currently amended] 38. The method of claim 37, wherein the bonding step is performed at a temperature of 125 [deg.] C. or higher.
    [39" claim-type="Currently amended] 38. The method of claim 37, wherein said isolation process is performed at a temperature condition of at least 150 &lt; 0 &gt; C.
    [40" claim-type="Currently amended] 40. The semiconductor chip burn-in test according to claim 37, 38 or 39, wherein the adhesive is a resin having a property of being half cured at 125 ° C or higher and isolated from the semiconductor chip at 150 ° C or higher. Way.
    [41" claim-type="Currently amended] 41. The method of claim 40 wherein the component of the adhesive is an epoxy or polyimide resin.
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    同族专利:
    公开号 | 公开日
    KR100470123B1|2005-02-04|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2001-09-01|Application filed by 동부전자 주식회사
    2001-09-01|Priority to KR20010053665A
    2003-03-10|Publication of KR20030020531A
    2005-02-04|Application granted
    2005-02-04|Publication of KR100470123B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR20010053665A|KR100470123B1|2001-09-01|2001-09-01|Board for burn-in test and fabrication method thereof, method for testing semiconductor chip by using it|
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